This invention relates generally to static latches employed in digital logic systems and more particularly, it relates to an improved CMOS latch for implementation as part of an integrated circuit so as to provide a greater operational reliability and higher speeds of operation.
It is generally known that in microprocessor designs storage units are required for temporarily storing digital information. One such type of storage unit is referred to as a static latch.
One implementation of such a static latch includes a pair of inverters, a feedback path coupling the output of one inverter to the input of the other inverter, and a CMOS transmission gate. The transmission gate may be formed of an N-channel MOS transistor and a P-channel MOS transistor having their common electrodes (source or drain leads) connected to a precharge/discharge data line and the other one of the common electrodes connected to an inverter's input node. The transmission gate is operable in response to a strobe signal for transferring data from the data line to the input node for latching. Each of the common electrodes is coupled to ground by a parasitic capacitance. One disadvantage of this type of static latch is encountered when a low voltage logic state is stored and a floating high logic state is written which causes a charge-sharing effect between the parasitic capacitances, thereby reducing the high voltage level of the logic state at the input node. Consequently, a problem of reliability in its operation is experienced when the high voltage level at the input node fails to reach the trip point of the latch. The larger the size of the devices in the latch that is required to achieve a given performance, the greater is the high voltage level reduction due to this charge-sharing phenomenon.
It would therefore be desirable to provide an improved CMOS latch which eliminates the lowering of the high voltage level of the data bus line caused by charge-sharing effects. It would also be expedient to provide a CMOS latch which operates at higher speeds so as to reduce logic delays.